// -----------------------------------------------------------------------------
// Copyright (c) 2014-2023 All rights reserved
// *********************************************************************************
// Project Name : CLA
// Author       : DFY
// File Name    : C_gen.v
// Abstract     : c3/c7/11/15
module C_gen (
	input		[3:0]	gm,  //	
	input 		[3:0]	pm,	//  
	input 				cin,// 配合级联

	output 				c3,// 配合级联
	output 				c7,// 配合级联
	output 				c11,// 配合级联
	output 				c15// 配合级联
);

//=================================================================================
// Body
//=================================================================================

assign c3  = gm[0]|pm[0]&cin;
assign c7  = gm[1]|pm[1]&gm[0]|pm[2]&pm[0]&cin;
assign c11 = gm[2]|gm[1]&pm[2]|gm[0]&pm[2]&pm[1]|cin&pm[2]&pm[1]&pm[0];
assign c15 = gm[3]|gm[2]&pm[3]|gm[1]&pm[3]&pm[2]|gm[0]&pm[3]&pm[2]&pm[1]|cin&pm[3]&pm[2]&pm[1]&pm[0];

endmodule 
